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features full cmos, 6t cell high speed (equal access and cycle times) ? 8/10/12/15/20/25/35/70/100 ns (commercial) ? 10/12/15/20/25/35/70/100 ns(industrial) ? 12/15/20/25/35/45/70/100 ns (military) low power operation output enable and dual chip enable control functions single 5v10% power supply data retention with 2.0v supply, 10 a typical current (ft6264l military) common data i/o fully ttl compatible inputs and outputs standard pinout (jedec approved) ? 28-pin 300 mil plastic dip, soj ? 28-pin 600 mil plastic dip (70 & 100ns) ? 28-pin 300 mil sop (70 & 100ns) ? 28-pin 300 mil ceramic dip ? 28-pin 600 mil ceramic dip ? 28-pin 350 x 550 mil lcc ? 32-pin 450 x 550 mil lcc ? 28-pin cerpack description the ft6264 is a 65,536-bit ultra high-speed static ram organised as 8k x 8. the cmos memory requires no clocks or refreshing and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. with battery backup, data integrity is maintained with supply voltages down to 2.0v. current drain is typically 10 a from a 2.0v supply. functional block diagram pin configurations 1519b dip (p5, p6, c5, c5-1, d5-1, d5-2), soj (j5), cerpack (f4), sop(s6) see page 7 for lcc pin configurations access times as fast as 8 nanoseconds are available, permitting greatly enhanced system operating speeds. the ft6264 is available in 28-pin 300 mil dip and soj, 28- pin 600 mil plastic and ceramic dip, 28-pin 350 x 550 mil lcc, 32-pin 450 x 550 mil lcc, and 28-pin cerpack. the 70ns and 100ns ft6264s are available in the 600 mil plastic dip. ultra high speed 8k x 8 static cmos rams ft6264(l) 9(6'3urwhfwlrq rev 1.8 1/17 2012 a ll data sheet.com
maximum ratings (1) symbol parameter value unit v cc power supply pin with C0.5 to +7 v respect to gnd terminal voltage with C0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature C55 to +125 c symbol parameter value unit t bias temperature under C55 to +125 c bias t stg storage temperature C65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce 1 v ih or mil. ce 2 v il , ind./coml. v cc = max, f = max., outputs open ___ ___ 40 30 ___ ___ ___ ___ 25 15 40 n/a 1 n/a ma ma ___ ___ ce 1 v hc or mil. ce 2 v lc , ind./coml. v cc = max, f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 grade (2) ambient temperature gnd v cc 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% C55c to +125c military symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = C18 ma i ol = +8 ma, v cc = min. i oh = C4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc ind./coml. v cc = max., ce = v ih , mil. v out = gnd to v cc ind./coml. ft6264 min 2.2 C0.5 (3) v cc C0.2 C0.5 (3) 2.4 C10 C5 C10 C5 max v cc +0.5 0.8 v cc +0.5 0.2 C1.2 0.4 +10 +5 +10 +5 ft6264l min max 2.2 C0.5 (3) v cc C0.2 C0.5 (3) 2.4 C5 n/a C5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 C1.2 +5 n/a +5 n/a unit v v v v v v v a a notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than C3.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. typ. industrial commercial C40c to +85c 0c to +70c )7/ rev 1.8 2/17 2012 a ll data sheet.com
data retention characteristics (ft6264l, military temperature only) typ.* max symbol parameter test condition min v cc =v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current 10 15 200 300 a t cdr chip deselect to 0 ns data retention time t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce 1 = v il , ce 2 = v ih , oe = v ih power dissipation characteristics vs. speed data retention waveform ce 1 v cc C 0.2v or ce 2 0.2v, v in v cc C 0.2v or v in 0.2v symbol parameter temperature range -8 -10 -12 -15 -20 -25 -35 45 -70 -100 unit commercial 200 180 170 160 155 150 145 n/a 130 125 ma industrial n/a 190 180 170 160 155 150 n/a 145 140 ma military n/a n/a 180 170 160 155 150 145 145 145 ma dynamic operating current* i cc )7/ rev 1.8 3/17 2012 a ll data sheet.com
ac electrical characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) notes: 5. we is high for read cycle. 6. ce 1 is low, ce 2 is high and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce 1 transition low and ce 2 transition high. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. timing waveform of read cycle no. 1 ( oeoe oeoe oe controlled) (5) min max min max min max min max min max min max min max min max min max min max t rc read cycle time 8 1012152025354570100ns t aa address access time 8 1012152025354570100ns t ac chip enable access time 8 1012152025354570100ns t oh output hold from address change 3333333333ns t lz chip enable to output in low z 2222222222ns t hz chip disable to output in high z 567881015203545ns t oe output enable low to data valid 5679101318203545ns t olz output enable low to low z 2222222222ns t ohz output enable high to high z 567991215203545ns t pu chip enable to power up time 0000000000ns t pd chip disable to power down time 8 101215202020253545ns symbol parameter -8 -10 -12 -15 -20 -25 unit -35 -45 -70 -100 )7/ rev 1.8 4/17 2012 a ll data sheet.com
timing waverform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( cece cece ce 1 , ce 2 controlled) (5,7,10) notes: 9. read cycle time is measured from the last valid address to the first transitioning address. 10. transitions caused by a chip enable control have similar delays irrespective of whether ce 1 or ce 2 causes them. ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) min max min max min max min max min max min max min max min max min max min max t wc write c ycle t ime8 1012152025354570100ns t cw chip enable time to end of write 6 7 8 12 15 18 25 33 50 70 ns t aw address valid to end of write 7 8 10 12 15 18 25 33 50 70 ns t as address set-up time 0000000000ns t wp write pulse width 7 8 9 12 15 18 20 25 40 50 ns t ah address hold time 0000000000ns t dw data valid to end of write 6 7 8 9 111315203040 ns t dh date h old t ime0000000000ns t wz write enable to output in high z 677781014183040ns t ow output active from end of write 3333333333ns symbol parameter -8 -10 -12 -15 -20 -25 unit -35 -45 -70 -100 )7/ rev 1.8 5/17 2012 a ll data sheet.com
notes: 11. ce 1 and we must be low, and ce 2 high for write cycle. 12. oe is low for this write cycle to show t wz and t ow . 13. if ce 1 goes high, or ce 2 goes low, simultaneously with we high, the output remains in a high impedance state. timing waveform of write cycle no. 2 ( cece cece ce controlled) (11) 14. write cycle time is measured from the last valid address to the first transitioning address. timing waveform of write cycle no. 1 ( wewe wewe we controlled) (11) )7/ rev 1.8 6/17 2012 a ll data sheet.com
mode cece cece ce 1 ce 2 oeoe oeoe oe wewe wewe we i/o power standby h x x x high z standby standby x l x x high z standby d out disabled l h h h high z active read l h l h d out active write l h x l high z active ac test conditions input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 truth table figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: because of the high speed of the ft6264/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). lcc (l5) "ls" - special pin-out lcc pin configurations lcc (l6) lcc (l5) "l" - standard pin-out )7/ rev 1.8 7/17 2012 a ll data sheet.com
n/a = not available selection guide the ft6264 is available in the following temperature, speed and package options. the ft6264l is available only over the military temperature range. ordering information 8 1012152025354570100 plastic dip (300 mil) -8pc -10pc -12pc -15pc -20pc -25pc -35pc n/a n/a n/a plastic dip (600 mil) n/a n/a n/a n/a n/a n/a n/a n/a -70p6c -100p6c plastic s oj -8jc -10jc -12jc -15jc -20jc -25jc -35jc n/a n/a n/a plastic sop n/a n/a n/a n/a n/a n/a n/a n/a -70snc -100snc industrial plastic dip (300 m il) n/a -10pi -12pi -15pi -20pi -25pi -35pi n/a n/a n/a plastic dip (600 mil) n/a n/a n/a n/a n/a n/a n/a n/a -70p6i -100p6i plastic soj n/a -10ji -12ji -15ji -20ji -25ji -35ji n/a n/a n/a plastic sop n/a n/a n/a n/a n/a n/a n/a n/a -70sni -100sni speed (ns) temperature range package commercial ft6264 l x x x m5004 x )7/ rev 1.8 8/17 2012 a ll data sheet.com
8 1012152025354570100 side brazed dip n/a n/a -12cm -15cm -20cm -25cm -35cm -45cm -70cm -100cm cerdip (300 mil) n/a n/a -12dm -15dm -20dm -25dm -35dm -45dm -70dm -100dm cerdip (600 mil) n/a n/a -12dwm -15dwm -20dwm -25dwm -35dwm -45dwm -70dwm -100dwm cerpack n/a n/a -12fm -15fm -20fm -25fm -35fm -45fm -70fm -100fm 28-pin lcc n/a n/a -12lm -15lm -20lm -25lm -35lm -45lm -70lm -100lm 28-pin lcc ** n/a n/a -12lsm -15lsm -20lsm -25lsm -35lsm -45lsm -70lsm -100lsm 32-pin lcc n/a n/a -12l32m -15l32m -20l32m -25l32m -35l32m -45l32m -70l32m -100l32m side brazed dip n/a n/a -12cmb -15cmb -20cmb -25cmb -35cmb -45cmb -70cmb -100cmb cerdip (300 mil) n/a n/a -12dmb -15dmb -20dmb -25dmb -35dmb -45dmb -70dmb -100dmb cerdip (600 mil) n/a n/a -12dwmb -15dwmb -20dwmb -25dwmb -35dwmb -45dwmb -70dwmb -100dwmb cerpack n/a n/a -12fmb -15fmb -20fmb -25fmb -35fmb -45fmb -70fmb -100fmb 28-pin lcc n/a n/a -12lmb -15lmb -20lmb -25lmb -35lmb -45lmb -70lmb -100lmb 28-pin lcc ** n/a n/a -12lsmb -15lsmb -20lsmb -25lsmb -35lsmb -45lsmb -70lsmb -100lsmb 32-pin lcc n/a n/a -12l32mb -15l32mb -20l32mb -25l32mb -35l32mb -45l32mb -70l32mb -100l32mb military processed * speed (ns) military temperature temperature range package selection guide (continued) * military temperature range with mil-std-883 m5004 ** special pinout n/a = not available )7/ rev 1.8 9/17 2012 a ll data sheet.com
pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c5 28 (300 mil) 0.300 bsc 0.100 bsc side brazed dual in-line package (300 mils) pkg # # pins symbol min max a-0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.490 e 0.500 0.610 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - c5-1 28 (600 mil) 0.600 bsc 0.100 bsc side brazed dual in-line package (600 mils) )7/ rev 1.8 10/17 2012 a ll data sheet.com
cerdip dual in-line package pkg # # pins symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.490 e 0.500 0.610 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d5-1 28 (600 mil) 0.600 b sc 0.100 b sc cerdip dual in-line package pkg # # p ins symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d5-2 28 (300 mil) 0.300 bsc 0.100 bsc )7/ rev 1.8 11/17 2012 a ll data sheet.com
pkg # # pins symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e e e1 0.292 0.300 e2 q0.025- j5 28 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc soj small outline ic package pkg # # pins symbol min max a 0.060 0.090 b 0.015 0.022 c 0.004 0.009 d-0.730 e 0.330 0.380 e k 0.005 0.018 l 0.250 0.370 q 0.026 0.045 s-0.085 s1 0.005 - f4 28 0.050 bsc cerpack ceramic flat package )7/ msl level: 3 rev 1.8 12/17 2012 a ll data sheet.com
pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 d2 d3 - 0.458 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne l6 32 0.300 bsc 0.150 bsc 0.020 ref 7 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref rectangular leadless chip carrier rectangular leadless chip carrier pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 b sc 0.200 b sc 0.050 b sc 0.040 ref l5 28 0.200 b sc 0.100 b sc )7/ rev 1.8 13/17 2012 a ll data sheet.com
pkg # # pins symbol min max a 0.090 0.200 a1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 c 0.008 0.012 d 1.380 1.480 e1 0.485 0.550 e 0.600 0.625 e eb l 0.100 0.200 0 15 p6 28 (600 mil) 0.100 bsc 0.600 typ plastic dual in-line package (600 mils) pkg # # pins symbol min max a-0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p5 28 (300 mil) plastic dual in-line package (300 mils) )7/ msl level: 3 msl level: 3 rev 1.8 14/17 2012 a ll data sheet.com
pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 d2 d3 - 0.458 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne l6 32 0.300 bsc 0.150 bsc 0.020 ref 7 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref rectangular leadless chip carrier rectangular leadless chip carrier pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 b sc 0.200 b sc 0.050 b sc 0.040 ref l5 28 0.200 b sc 0.100 b sc )7/ rev 1.8 15/17 2012 a ll data sheet.com
ashley crt, henley, marlborough, wilts, sn8 3rh uk tel: +44(0)1264 731200 fax:+44(0)1264 731444 e-mail sales@forcetechnologies.co.uk www.forcetechnologies.co.uk life support applications force technologies products are not designed for use in life support appliances, devices or systems where malfunction of a force technologies product can reasonably be expected to result in a personal injury. force technologies customers using or selling force technologies products for use in such applications do so at their own risk and agree to fully indemnify force technologies for any damages resulting from such improper use or sale. all trademarks acknowledged copyright force technologies ltd 20 unless otherwise stated in this scd/data sheet , force technologies ltd reserve the right to make changes, without notice, in the products, includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. force technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified. rev 1.8 16/17 2012 a ll data sheet.com
revisions document number : sram115 document title : ft 6264 ultra high speed 8k x 8 static cmos rams rev. issue date orig. of change description of change or 1997 m.s new data sheet 1.1 oct-05 m.s data sheet review 1.2 jun-06 m.s added 28-pin ceramic dip 1.3 aug-06 m.s added lead free designation 1.4 aug-06 m.s added "ls" - special pin-out 1.5 aug-06 m.s updated soj package information 1.6 jun-07 m.s corrected sop package details 1.7 jan-11 b.s new logos added 1.8 feb-12 b.s added msl levels rev 1.8 17/17 2012 a ll data sheet.com

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